High-bit-rate serial connections—whether electrical or optical—as a rule require that the bit stream to be transmitted is D[irect]C[urrent]-balanced or DC-balanced. Fundamental circuit parts in such a transmission path are conceptually dependent on this property of the DC-balance of the data stream in order to function.
In order to convert any data stream, which as a rule is DC-unbalanced and thus initially not pre-conditioned for optical transmission, into a DC-balanced data stream, transcoding schemes can be employed which though technically manageable nevertheless require additional circuitry on the one hand and on the other, distinctly lower the net bit rate due to the transcoding overhead which is being created.
For example, for an overhead of twenty percent a net bitrate of five Gigabit per second (5 Gbit/s) in the protocol layer turns into a gross bitrate of six Gigabit per second (6 Gbit/s) in the physical layer.
The basis used for such 5b/6b blocks is, in the main, the instructions and the table by Albert X. Widmer (IBM Research Division). For the relevant technological background see the publication U.S. Pat. No. 6,911,921 B2 of the state of the art.
Apart from a data overhead being created the transcoding operation also increases energy consumption of the entire transmission path. With very high bitrates in particular internal data preparation accounts for a considerable share in the overall energy consumption so that the use of such transcoding schemes is not always a preferred option.
But since the data stream, which initially is not pre-conditioned for optical transmission is, as a rule, DC-unbalanced, meaning that because logical “1” and logical “0” do as a rule not occur evenly distributed in the incoming data stream during the optical transmission, conventionally used extraction methods are unable to determine unequivocally that voltage level of the incoming data stream, which defines the middle between the logical “1” and the logical “0”.
The provision of a D[irect]C[urrent] current compensation for ascertaining a decision- or differentiating threshold between high optical input power (logical “1”) and low optical input power (logical “0”) serves the purpose of ensuring that the remaining current, i.e. the current resulting from the input current minus the DC compensation current is bipolar, i.e. has either a positive current direction (logical “1” minus DC compensation current) or a negative current direction (logical “0” minus DC compensation current).
By way of example, as regards the technological background of DC current compensation, attention may be drawn to pages 140ff of the textbook “Broadband Circuits of Optical Fiber Communication” by Eduard Säckinger, the first edition of which was published on 8 Apr. 2005 by John Wiley & Sons. In here FIG. 5.23 shows the circuit arrangement for such a DC current compensation for a differential input stage.
DC current compensation can now be automatically regulated on the basis of the input data, but this is connected with a certain amount of necessary circuitry which delays processing of the incoming signals.